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| CCD Delay Line Series MN38662S NTSC-Compatible CCD Video Signal Delay Element Overview The MN38662S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 681 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38662S samples the input using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. When the switch input is "H" level, the MN38662S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.53496 MHz or 9.545454 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC VSS3 VDD3 VINC1 N.C. VINVC VGC1 VO1C VDD1 VSS1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 XIV PCOUT & VCOIN -VBB VSS2 VDD2 VINVY SW VINC2 VGC2 VO2Y ( TOP VIEW ) SOP020-P-0300 Features Single 4.8 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38662S for signal processing Applications Video cameras 1 MN38662S Block Diagram CCD Delay Line Series VGC1 16 V DD2 17 V SS2 10 14 Bias circuit Clamp circuit Mode switch Booster circuit Voltage generator VINVC 6 L H Charge input block Charge input block 79-stage analog shift register 3-stage analog shift register 3-stage analog shift register 79-stage analog shift register H L H 602-stage analog shift register L H Charge detector Voltage generator 8 VINC1 4 H L Resampling output amplifier 12 VO1C 11 VO2Y oS driver oR driver oSH driver -VBB 18 3 2 9 VINVY 15 L H L H 602-stage analog shift register L H Charge detector Resampling output amplifier Charge input block Charge input block VINC2 13 H L XIV 20 L H XIC 1 Waveform amplifier adjustment block 1/3rd frequency divider L Waveform adjustment block o1 driver L H VCO Timing adjustment L H VSS o2 driver Phase comparator 19 2 PCOUT & VCOIN 7 Substrate bias generator VGC2 VDD1 VDD3 VSS1 VSS3 SW CCD Delay Line Series Application Circuit Example MN38662S + 4.8V - 10F 4.8V or GND 0.01F VGC1 0.01F 12 VGC2 0.1 VDD1 16 VDD2 10 VSS1 0.1 17 VSS2 VDD3 0.1 VSS3 14 SW 3 2 9 Bias circuit Clamp circuit Mode switch Booster circuit 7 Voltage generator Signal input VINVC 6 -+ 0.47F Signal input VINC1 4 -+ 0.47F Signal input VINVY 15 -+ 0.47F Signal input VINC2 13 -+ 0.47F Clock input XIV 20 1000pF Clock input XIC 1000pF L H H L Charge input block Charge input block 79-stage analog shift register 3-stage analog shift register 3-stage analog shift register 79-stage analog shift register H L H 602-stage analog shift register L H Charge detector Voltage generator 8 VO1C Signal output (1C) Resampling output amplifier L H H L L H L H 602-stage analog shift register L H oS driver Charge detector Resampling output amplifier 11 VO2Y Signal output (2Y) Charge input block Charge input block 1 Waveform amplifier adjustment block 1/3rd frequency divider L Waveform adjustment block o1 driver oR driver oSH driver VCO Timing adjustment L H 19 o2 driver L H Phase comparator Substrate bias generator -VBB 18 PCOUT & VCOIN 0.01F 0.01F 820 1000pF Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 3 MN38662S Package Dimensions (Unit:mm) SOP020-P-0300 CCD Delay Line Series 12.600.20 20 11 1.100.20 5.500.20 7.700.30 0.15 -0.05 +0.10 0 to 10 0.30min. 1 10 (0.6) 1.27 0.400.10 SEATING PLANE 4 0.100.10 1.90max. 1.500.20 |
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